When we compile a program, the compiler performs certain
optimizations while converting it to the machine code. Even while
running the program the processor may also rearrange the machine code
for optimization. The rearrangement also have some rules. The strong
memory models provide sequential consistency, hence they do not
rearrange the instructions. But the processors with relax memory model
permits to reorder load and store (read/write) operations.
The
compiler reordering depends on the optimization. Example compiling
programs with -O0 optimization will not get reordered, but programs
compiled with -O2 optimization may get reordered. It also depends on
your machine's architecture, like x86/64 supports TSO whereas IA-64
supports all reorderings expect reordering the dependent loads.
Relax memory models
1. Total Store Order(TSO)
It is a comparatively stricter model. It allows only store-load reordering. That
means if there is a sequence of instructions in which a load operation
is followed by store operation, it can be rearranged as load-store.
However,
the rearrangement only occurs if the events(load and store) are
happening to different memory location. No rearrangement in case of
operations on the same memory.
Store A → Load B
Load B Store A
It does not allow load-load, load-store and store-store reordering.
2. Partial Store Order(PSO)
It is a weaker model. It allows store-store and store-load reordering. Meaning if there is a sequence of instructions in which a load operation
is followed by store operation or a store operation followed by a store operation, it can be rearranged.
However, the rearrangement only occurs if the events(load and store or store and store) are
happening to different memory location. No rearrangement in case of
operations on the same memory.
Store A → Load B
Load B Store A
Store A → Store B
Store B Store A
It does not allow load-load, load-store reordering.
3. Weakest Memory Model
It supports all four re-orderings.